Various energy saving measures are being studied and developed at the global level for the purpose of global environment protection. In this trend, many countries have begun to discuss about enactment of legislation to mandate energy saving and reduction of carbon-dioxide emissions.
In general, many people will think that such energy saving measures apply to energy consumption arising from fields of transportation, logistics, and manufacture. On the other hand, also attracting attention is the increase in energy consumption by electronic equipment such as computers and servers, and information communication equipment and network infrastructure.
In the case of electronic equipment such as computers and servers, the equipment is often kept in the so-called stand-by state for a relatively long period of time. This shows that a relatively long period of time is spent without arithmetic processing. Therefore, reduction of the power consumption during the stand-by state effectively helps reducing the average power consumption, and hence reducing the carbon-dioxide emissions.
As for information communication equipment, however, such equipment should be always kept in the data communicable state even though the communication system has been changed from analog to digital. Therefore, unlike the electronic equipment such as computers and servers, the information communication equipment can not pre-requisitely dispense with the stand-by state. In other words, the average power consumption cannot be reduced in the information communication equipment unless the stationary or ordinary operating power is reduced.
As a result, the effort of power reduction is mainly pursued from the viewpoint of device technologies aiming at reduction of the operating voltage accompanied by the increased degree of integration and miniaturization of electronic components.
However, the operating voltage of such electronic components has already been reduced to less than one volt. Accordingly, in an actual trend, a reduction rate of operating voltage due to miniaturization of electronic components now becomes slow, and so the effect obtained by increased degree of integration tends to become slow down.
This has made it difficult to achieve significant reduction of power consumption, only by miniaturization or increased degree of integration of electronic components.
Advanced miniaturization of electronic components (for example, below 90 nm) has increased the leaked current up to a non-negligible level. For this reason, the power consumption during the stand-by state is being significantly increased in spite of research efforts made by device vendors using the device technologies.
On the other hand, various researches are being made also from the viewpoint of circuitry designs. Specifically, efforts of reducing the power consumption are slowly but progressively pursued by employing an asynchronous circuit architecture and method using no clocks in place of a clock synchronization circuit architecture and method currently mainly used in designing internal circuit configuration of electronic components.
This technique aims to reduce the average power consumption by reducing the stationary operating power and the power consumption during the stand-by state. However, special development tools are required for design and verification in order to employ such asynchronous circuit architecture and method as a development method of common electronic components such as ASICs and FPGAs, but such tools are not easily accessible yet for developers in general.
A packet processing device related to the present invention will be described with reference to FIG. 6.
FIG. 6 is a block diagram showing an example of a packet processing device provided in packet communication equipment which has a variable input traffic capacity.
In a packet processing device 1000 shown in FIG. 6, a packet input to a packet input terminal 1001 is temporarily stored in an input packet buffer 1002 and then transferred to a first packet processor 1011.
The first packet processor 1011 performs first packet processing in response to the packet and then outputs a first processed packet to the following stage.
The first processed packet output from the first packet processor 1011 is transferred to a second packet processor 1012 via a first clock retiming unit 1021.
The second packet processor 1012 performs second packet processing in response to the first processed packet and then outputs a second processed packet to the following stage.
The second processed packet output from the second packet processor 1012 is transferred to a third packet processor 1013 via a second clock retiming unit 1022.
The third packet processor 1013 performs third packet processing in response to the second processed packet and then outputs a third processed packet to the following stage.
The third processed packet output from the third packet processor 1013 is temporarily stored in an output packet buffer 1003 and then supplied as a processed output packet through a packet output terminal 1004 to the outside of the packet processing device 1000.
On the other hand, power supply for the packet processing device 1000 is provided to a power input unit 1051. The power input unit 1051 outputs the input power supply to a power supply unit 1052.
The power supply unit 1052 delivers electric power to the respective devices and units of the packet processing system 1000 at currents and voltages suitable for use in the devices and units.
Japanese Laid-Open Patent Publication No. 2003-158771 (Patent Document 1) and Japanese Laid-Open Patent Publication No. 2002-182807 (Patent Document 2) are known as prior art documents related to the present invention.
In Patent Document 1, the following three functions are set forth as its basic features in claim 1.
1) First reception means for constantly monitoring reception of a notification signal notifying arrival of a packet and reception of a packet, and for receiving the notification signal or the packet;
2) Second reception means for receiving a packet with a greater reception power than the first reception means; and
3) A reception controller operable in a state of receiving no packet so as to cause the first reception means to monitor reception of a notification signal or packet. When the first reception means receives a notification signal or packet, the reception controller switches from the first reception means to the second reception means.
According to the technique described in Patent Document 1, the power consumption can be reduced by constantly monitoring reception of a packet or a notification signal notifying arrival of a packet and by switching between two reception means, namely first and second reception means.
Patent Document 2 discloses a condition detector and a power table which has a plurality of power control registers. The condition detector rewritably stores a plurality of operating conditions (for example, a comparison address given to a program counter) and judges whether a current condition of a processor is matched with either one of the operating conditions. Either one of the power control registers is selected by an index signal which is produced in response to a result of the judgment. The power control information selected by the index signal is delivered to a voltage and clock controller to control power consumption of an object circuit block.
According to Patent Document 2, since the power control information in the power table and the various processor operating conditions are rewritable, the user is allowed to define the low-power-consumption operation of the processor in detailed manner. Further, the provision of the condition detector makes it possible to provide an event-driven-type power control device capable of relieving the burden in programming.